The present invention relates to a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device comprising a capacitor element and having high process compatibility with a MIS transistor and a method for fabricating the same.
In recent years, as a semiconductor integrated circuit device has become higher in integration and functionality, the integration thereof with an analog circuit or the like has become increasingly important. Of the analog circuit, on the other hand, enhanced process compatibility with a MIS transistor in addition to the formation of a stable capacitor element has been requested.
A conventional MIS transistor including a capacitor element has been formed by fabrication steps as shown in FIGS. 10A to 10D.
That is, as shown in FIG. 10A, an isolation insulating film 102 is formed in a semiconductor substrate 101. Then, a gate insulating film (not shown) and a gate electrode 103 composed of a silicon film are formed on the surface of the semiconductor substrate 101. In a typical case, another gate electrode 103 is also formed on the isolation insulating film 102.
Next, as shown in FIG. 10B, a planarized interlayer insulating film 104 is formed. Subsequently, the capacitor element composed of a lower electrode 105, a capacitor insulating film 106, and an upper electrode 107, each of which has been patterned, is formed on the interlayer insulating film 104.
Then, as shown in FIG. 10C, an interlayer insulating film 108 is further formed. Thereafter, contact holes 110, 111, and 112 are formed in specified regions. Then, as shown in FIG. 10D, a metal 113 is buried in each of the contact holes to connect the lower and upper electrodes 105 and 107 of the capacitor element and the gate electrodes 103 of the MIS transistor to respective wirings 114, whereby the MIS transistor including the capacitor element is completed.
In accordance with the conventional method, however, the lower and upper electrodes 105 and 107 of the capacitor element are formed after the formation of the gate electrode 103 so that the fabrication steps thereof are complicated. In addition, a thermal process for forming the capacitor element is performed after the formation of the MIS transistor. As a result, the problem has been encountered that the impurity profile of the transistor fluctuates.
In solving the problem, a method for rendering the steps of forming the capacitor element compatible with the steps of forming the MIS transistor is useful. Japanese Laid-Open Patent Publication No. 2003-234415 discloses a fabrication method aiming at achieving such process compatibility, which will be described herein below with reference to the step cross-sectional views shown in FIGS. 11A to 11D.
First, as shown in FIG. 11A, isolation insulating films 102a and 102b having different thicknesses are formed in the surface of the semiconductor substrate 101. Then, a gate insulating film (not shown) and the gate electrode 103 composed of a silicon film are formed on the surface of the semiconductor substrate 101, while the lower electrode 105, which is composed of the same silicon film as composing the gate electrode 103, is also formed simultaneously on the thicker isolation insulating film 102b. In a typical case, the other electrode 103 is also formed on the isolation insulating film 102a. 
Next, as shown in FIG. 11B, the planarized interlayer insulating film 104 is formed. Then, as shown in FIG. 11C, the interlayer insulating film 104 on the lower electrode 105 is etched back till the thickness of the interlayer insulating film 104 is reduced to a value which allows the capacitor element to have a desired capacitance value. Subsequently, the contact holes 110 and 111 are formed in specified regions.
Finally, as shown in FIG. 11D, thc metal 113 is buried in each of the contact holes. Then, the wirings 114 to be connected to the lower electrode 105 of the capacitor element and to the gate electrode 103 of the MIS transistor are formed, while the upper electrode 115 is formed simultaneously, whereby the MIS transistor including the capacitor element is completed.
In accordance with the method, the process steps can be simplified by forming the lower and upper electrodes 105 and 115 of the capacitor element simultaneously with the gate electrodes 103 of the MIS transistor and the wirings 114.
Moreover, by preliminarily forming the isolation insulating film 102b on which the capacitor element is formed such that it is sufficiently thick, the thickness of the interlayer insulating film 104 between the gate electrode 103 formed on the isolation insulating film 102a and the interconnection 114 can be maintained at a value which allows a parasitic capacitance to be ignored when a capacitor insulating film having a desired capacitance value is formed on the lower electrode 105 by etching back the interlayer insulating film 104. Accordingly, even when the process steps are simplified, the characteristics of the semiconductor integrated circuit device are not degraded.
In addition, the capacitor element is formed simultaneously in the steps needed to form the MIS transistor. This prevents the occurrence of the problem that the impurity profile of the transistor fluctuates.